To remain competitive in today's ASIC (application specific integrated circuit) market, circuit designers are becoming increasingly sensitive to maximizing circuit performance by utilizing the last few nanoseconds (ns) or even picoseconds (ps) of performance a given technology has to offer. This places increasingly higher demands on the accuracy of the simulation tool used for predicting timing delays and output transition times. However, with each increase in the accuracy of predicting timing delays and output transition times comes an increase in simulation time.
The desired balance between accuracy and simulation time plays a major role in determining the simulation method used. chosen where calibration points as a function of Tx and Cload are obtained to characterize the circuit performance. To account for variations in voltage, temperature, and process, the industry standard method utilizes multiplicative derating factors to scale the propagation delay (or output transition time) from the base operating conditions. The multiplicative derating factors used in the industry today can result in varying degrees of timing inaccuracies.
To account for variations in two of the three variables that define an operating condition (i.e. voltage and temperature), a multiplicative derating factor for each variable is used. These derating factors, sometimes referred to as k-factors, are used to scale the base delay, as shown below in equation 1, where the base delay is the delay at the base operating condition. ##EQU1## Note that the third variable, process, is typically defined as part of the base line condition. This requires that calibration points be generated for each case (i.e. best, nominal, and worst), and that each case defines its own unique table or equation, thus eliminating the need for a process derating factor. Another prior art approach defines worst For example, one prior art approach resulting in extremely accurate timing is the use of an analog circuit simulator. Although the required simulation time when using an analog circuit simulator may be tolerable for small circuits, using an analog simulator quickly becomes prohibitive for larger circuit layouts.
An alternative prior art approach is the use of a digital timing simulator with a method that greatly reduces simulation time, while achieving the desired level of accuracy in predicting input to output delay and output transmission rates. To achieve this, the prior art methods encode calibration points obtained from an analog simulator in a way unique to the particular method used. For example, some prior art methods use the calibration points as table entries and then use some form of interpolation to predict values between the calibration points, while others use the calibration points as curve fitting data for generating multiple term equations that are used in predicting delay and transition times.
Whether using a table or an equation, most prior art methods, at a given operating condition (i.e. voltage, temperature and process), become a two dimensional function of the input transition time, Tx, and the output load capacitance, Cload. A base operating condition is typically case as the base process condition and then uses a process derating factor to calculate the nominal and best case process delays.
The K.sub.V and K.sub.T variables are the k-factors used to account for variations in operating conditions. By assuming K.sub.V is independent of temperature and K.sub.T is independent of voltage, the following equations can be used to express K.sub.V and K.sub.T as functions of voltage and temperature respectively, as shown below in equations 2 and 3. ##EQU2##
Note that two assumptions are made in the way k-factors are used. The first assumption is that the change in base delay to a change in one operating condition parameter is independent of the other parameter. Although this assumption is valid for first order approximations, there have been some second order coupling effects observed between voltage and temperature. The second assumption is that the change in base delay to a change in either voltage or temperature is linear. Therefore, if an x change in voltage causes a y change in delay, then a 2x change in voltage will cause a 2y change in delay. Although this assumption is valid for small-signal variations of V.sub.DD (i.e. +/-10%), some second order effects (and possibly third order effects) would be expected for greater variations of V.sub.DD (i.e. +/-30%).
Historically, values for K.sub.V and K.sub.T have been obtained during calibration by measuring the base delay at a single Tx-Cload characterization point and observing the change in delay caused by a change in voltage or temperature. These values are then used during simulation for all Tx-Cload combinations.
A salient characteristic of equations 2 and 3 is their intrinsic sensitivity to the magnitude of the delay at the base operating condition. For a given timing path, the base delay can vary greatly as a function of Cload and Tx. This is shown in FIG. 1. Note that negative delays can occur with large input transition times or light output loads when using a midpoint voltage threshold on both the input and output. FIG. 1 depicts the delay for a given timing path as a function of input transition time (Tx) and output loading capacitance (Cload). The delay values in FIG. 1 were obtained using an analog circuit simulator at the base voltage and temperature using a fast process (i.e. best case process). The region bounded by the contour lines illustrates the range of Tx-Cload combinations that result in delay magnitudes of less than 0.1 ns.
To illustrate the sensitivity of K.sub.V to the magnitude of the base delays shown in FIG. 1, delay values were acquired with an analog simulator over the same Tx-Cload range using a V.sub.DD that was 0.6 volts from the base operating condition. These delay values and the base values in FIG. 1 were used in equation 2 to obtain the range of K.sub.V values shown in FIG. 2. FIG. 2 illustrates the range of values obtained for K.sub.V using the base delays in FIG. 1 and changing 0.6 volts from the base operating condition. The region bounded by the contour lines in FIG. 2 represents the range of Tx-Cload combinations with a K.sub.V magnitude greater than two. A logarithmic scale was chosen for FIG. 2 in order to highlight the wide variation of K.sub.V values across the entire Tx-Cload range. Note that the contour of base delay values ranging from -0.1 to 0.1 nanoseconds in FIG. 1 shows a high degree of correlation with the erratic peak range of K.sub.V values in FIG. 2.
Due to the similarities of equations 1 and 2, the sensitivity of K.sub.T to the magnitude of the base delay is similar to FIG. 2. It can be seen from equation 2 that as the base delay asymptotically approaches zero the value for K.sub.V goes to infinity. In other words, K.sub.V is inversely proportional to the base delay. As technologies become faster (i.e. as base delays gets closer to zero), the sensitivity of K.sub.V to variations in delay will increase. This increase in sensitivity causes an increase in the variation of K.sub.V across the Tx-Cload range, which in turn increases the error when using one K.sub.V value for all Tx-Cload combinations. In other words, faster technologies will result in smaller propagation delays (i.e. smaller DELAY.sub.BASE), resulting in larger k-factors, which in turn leads to larger prediction errors.
Even when using a typical K.sub.V of -0.33, as shown in FIG. 3, the resultant errors are large. The contour lines in FIG. 3 indicate the very small region of Tx-Cload combinations that results in a digital simulation error of less than 10 ps.
One approach to reducing the errors associated with using a single K.sub.V and K.sub.T factor would be to generate K.sub.V and K.sub.T as functions of Tx and Cload. If we consider the Tx and Cload grid as a two dimensional spatial area, both K.sub.V and K.sub.T exhibit high spatial variations across this area. These high variations require a high degree of resolution in characterizing a k-factor across this grid, which in turn would increase the complexity of the equations needed.
A prior art approach which attempts to provide more accurate delay time estimates is found in U.S. Pat. No. 5,274,568, issued Dec. 28, 1993, to Blinne et al. (hereinafter "Blinne"). The method taught in Blinne adds a correction factor to a base delay time. However, Blinne uses the industry standard multiplicative derating factor to model process, temperature, and voltage effects both when calculating the base delay time and when calculating the correction factor. Because Blinne uses a multiplicative derating factor to model process, temperature, and voltage effects, Blinne does not teach nor suggest the present invention as claimed herein.
Consequently, it would be desirable to have a system and method for more accurately predicting timing delays and output transition times for integrated circuit logic cells. It would be desirable to have a system and method which is easy to use, and which increases accuracy without any significant increase in simulation time.